REAL3D R3D/100
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REAL3D Support Desk
Commercial Visual Systems
Lockheed Martin Information Systems Co.
MP-838
12506 Lake Underhill Rd.
Orlando, FL 32825 

Phone: 1-800-393-7730 or 407-826-3358
Fax: 407-826-3358 E-mail: [*]real3d@mmc.com

REAL3D is a Trademark of Lockheed Martin Information Systems 
Company 
PRODUCT INFORMATION:

[*]REAL3D is the name for a series of real-time graphics engines 
based on technology first developed for astronaut training and high 
performance mission rehearsal simulators. 

R3D/100 is the first 3-D graphics accelerator to bring true real-
time performance to the PC user. High throughput, high realism and 
sustained real-time response are delivered by an integrated geometry 
processor, graphics processor and texture processor. The floating 
point geometry processor transforms coordinates and clips to screen 
coordinates in silicon. The texture processor extracts and warps 
color texture maps (perspectively correct) in silicon. 

The R3D/100 was announced at the WINHEC '95 conference (March 1995) 
and will be available for limited release for qualified partners 
and application developers beginning Q4/95. Production shipments 
to U.S. and foreign customers will begin Q1/96. 
COMPANY INFORMATION:

Formed by the merger of Lockheed with Martin Marietta in 1995, Lockheed 
Martin is the world's largest defense, DOE, and NASA contractor. 
The Information Systems Company, part of Martin Marietta before the 
merger, employs 2,600. 
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SYSTEM OVERVIEW:
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The R3D/100 chip set consists of a Geometry Processor, Graphics Processor,
Texture Processor, Depth Buffer Controller, Frame Buffer Controller,
PCI Controller, and Video Output Controller. 

The geometry processor accelerates vertex transformations and clipping. 

The graphics processor provides true on-chip polygon rendering acceleration. 
Point, line and polygon primitives are hardware accelerated, with 
primitives accepted from the geometry processor or directly from 
the PCI controller. Other hardware accelerated functions include 
Gouraud shading, depth buffering, exponential fog, directed light 
source illumination, alpha testing, scissor and stipple masking, 
multi-pass anti-aliasing, and block read/writes. A full 32-bit RGBA 
internal color computational path is provided. 

The texture processor executes true perspective-corrected texture 
mapping and MIP-mapped level-of-detail selection in hardware. Rendering 
bandwidth is maximized by connecting the texture processor directly 
to texture buffer memory via an external I/O bus. Up to 8 MBytes 
of memory can be directly interfaced, and texture map sizes and formats 
from 32 x 32 to 512 x 512 and eight to 32 bits per texel are supported. 

The optional depth buffer controller stores non-displayed pixel (fragment) 
information such as depth (Z) values, stencil data and alpha data. 
For applications where each window pixel is written for each frame 
time a depth status flag eliminates the need to clear the depth buffer 
before each frame update. The 40 bit wide depth buffer can directly 
access up to 5 Mbytes of memory, providing needed scalability to 
meet specific price/performance goals. Block read/write and clear 
buffer operations are provided. 

Charged with storing RGB color data for each pixel (fragment), the 
frame buffer provides double buffering capability at the highest 
video resolution and color width. The frame buffer has a width of 
up to 24 bits and can directly access up to 10 Mbytes of memory. 
Block read/write and clear buffer operations are provided. 

The PCI controller, a 32-bit PCI Rev. 2.0 on-chip interface, boosts 
communications between the Host CPU and the R3D/100. No external 
glue logic is needed. The optimized interface performs single cycle 
transfers in target and master modes and provides DMA mastering capability 
for efficient and fast data transfer. Separate 32-bit input and output 
FIFOs provide highly efficient data buffering between the R3D/100 
graphics core and external devices. 

The video output controller provides an on-chip programmable video 
timing generator and 2-D/3-D video output control to standard DACs. 
The R3D/100 phase-locks to external 2-D hardware accelerators and 
internally multiplexes incoming RGB video before outputting to the 
DAC. The 3-D video output can occupy the full screen or maintain 
a proper window priority relationship with 2-D windows. 

[I]
UPDATE RATE:
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Update rate is highly dependent on other system design parameters; 
the chip set can support true real-time updates up to 76 Hz. 
TRANSPORT DELAY:

The geometry processor requires one update cycle, the graphics and 
other processors require another, and the frame buffer delay is an 
additional field time. 
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SYSTEM CAPACITY:
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POLYGONS PER CHANNEL:

Up to 750,000 three-edge polygons can be processed per second. Up 
to four-edge polygons (before clipping) are supported. Polygons may 
be Gouraud shaded, depth buffered, clipped, stenciled, alpha blended,
and rendered with MIP-mapped texturing. 
PIXEL FORMATS:

The video controller provides software programmable timing generation 
for a variety of video formats. Scalable screen resolution can be 
from 320 x 200 up to 1280 x 1024 with 16 or 24-bit true color. The 
system will support both interlaced and non-interlaced display configurations 
for a wide variety of display devices. 
PIXEL FILL RATE:

For 32-bit pixels, the R3D/100 can achieve a block move rate of 132 
MBytes/second. 
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TEXTURE:
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On-board storage of color and monochrome texture maps with eight 
through 24-bit RGB formats and up to eight bits of alpha for translucency 
is supported. 
TEXTURE MEMORY:

Up to eight MBytes of texture memory can be addressed by the chip 
set. Maps can be stored as monochrome intensities, indexed color,
or true RGBA color with 8, 16, or 32 bits per texel. 
MAP SIZES:

Texture maps can be any rectangular size, 2n x 2m , where m and n 
are less than or equal to eleven. Control of size and placement is 
made during database design. 
MAPS PER POLYGON:

One map per polygon is supported. 
TEXTURE PLACEMENT:
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Each polygon's vertices are linked to specific locations in the texture 
map. 
TEXTURE FEATURES:
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Full color information is stored in the texture map, and users are 
not limited to merely modulating between two discrete colors. 
TEXTURE MANAGEMENT:

A pixel's texturing is determined by one of several algorithms, the 
highest quality being trilinear interpolation. This provides linear 
smoothing between the adjacent texture elements (texels) and LODs. 
All possible LODs are stored in a MIP-mapped image pyramid, for simultaneous 
realtime access. All calculations are performed with the precision 
necessary to avoid texture aliasing, and prevent LOD "bow-wave" effects. 

TEXTURE PAGING:
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Support for dynamic texture map loading is provided. 
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PRIORITY TECHNIQUE:
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The R3D/100 uses a Z buffer on a per-pixel basis. The Z buffer has 
up to 24-bit precision. Layering of co-planar polygons and forced 
(high priority) polygons are available. 
LEVELS OF OCCULTING:

Since the R3D/100 is a Z buffer architecture, the number of occulting 
levels is only limited by the number of polygons being processed. 

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ANTI-ALIASING:
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Support for multi-pass anti-aliasing is provided. 
FOG IMPLEMENTATION:
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Fog level may be assigned per vertex, with bilinear interpolation 
performed to the pixel level. Alternately, fog may be calculated 
as an exponential function based on range per pixel. 
TRANSPARENCY:
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Translucent polygons are available. 
SHADING:
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Color intensity can be assigned per vertex, and interpolated to the 
pixel level to perform smooth shading. 

[*][I]
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To find out why real time graphics will never be the same again, 
just call 1-800-393-7730 or send email to [*]real3d@mmc.com
Created by [*]Jeff Potter
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